Regviz

Freescale Semiconductor /MKE14Z7 /FTM2 /SC

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Interpret as SC

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (000)PS0 (00)CLKS 0 (0)CPWMS 0 (0)RIE 0 (0)RF 0 (0)TOIE 0 (0)TOF 0 (0)PWMEN0 0 (0)PWMEN1 0 (0)PWMEN2 0 (0)PWMEN3 0 (0)PWMEN4 0 (0)PWMEN5 0 (0)PWMEN6 0 (0)PWMEN7

PWMEN1=0, PWMEN0=0, TOIE=0, PWMEN2=0, CPWMS=0, PWMEN6=0, PWMEN7=0, CLKS=00, PS=000, PWMEN4=0, PWMEN3=0, PWMEN5=0, RIE=0, TOF=0, RF=0

Description

Status And Control

Fields

PS

Prescale Factor Selection

0 (000): Divide by 1

1 (001): Divide by 2

2 (010): Divide by 4

3 (011): Divide by 8

4 (100): Divide by 16

5 (101): Divide by 32

6 (110): Divide by 64

7 (111): Divide by 128
CLKS

Clock Source Selection

0 (00): No clock selected. This in effect disables the FTM counter.

1 (01): System clock

2 (10): Fixed frequency clock

3 (11): External clock
CPWMS

Center-Aligned PWM Select

0 (0): FTM counter operates in Up Counting mode.

1 (1): FTM counter operates in Up-Down Counting mode.
RIE

Reload Interrupt Enable

0 (0): Reload interrupt is disabled.

1 (1): Reload interrupt is enabled.
RF

Reload Flag

0 (0): FTM counter did not reach a reload point.

1 (1): FTM counter reached a reload point.
TOIE

Timer Overflow Interrupt Enable

0 (0): Disable TOF interrupts. Use software polling.

1 (1): Enable TOF interrupts. An interrupt is generated when TOF equals one.
TOF

Timer Overflow Flag

0 (0): FTM counter has not overflowed.

1 (1): FTM counter has overflowed.
PWMEN0

Channel 0 PWM enable bit

0 (0): Channel output port is disabled

1 (1): Channel output port is enabled
PWMEN1

Channel 1 PWM enable bit

0 (0): Channel output port is disabled

1 (1): Channel output port is enabled
PWMEN2

Channel 2 PWM enable bit

0 (0): Channel output port is disabled

1 (1): Channel output port is enabled
PWMEN3

Channel 3 PWM enable bit

0 (0): Channel output port is disabled

1 (1): Channel output port is enabled
PWMEN4

Channel 4 PWM enable bit

0 (0): Channel output port is disabled

1 (1): Channel output port is enabled
PWMEN5

Channel 5 PWM enable bit

0 (0): Channel output port is disabled

1 (1): Channel output port is enabled
PWMEN6

Channel 6 PWM enable bit

0 (0): Channel output port is disabled

1 (1): Channel output port is enabled
PWMEN7

Channel 7 PWM enable bit

0 (0): Channel output port is disabled

1 (1): Channel output port is enabled

Links

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Register License

Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or\n other materials provided with the distribution.\n o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS “AS IS” AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data